1. Field of the Invention
The present invention relates to a serial/parallel converter that enables fast processing with low current consumption.
2. Related Arts
A serial/parallel converter is frequently employed in an integrated semiconductor circuit Such a serial/parallel converter is, for example, one by which a plurality of serially input address signals from a system are output in parallel internally. This converter is employed for a system having an extremely high transfer rate, such as 800 Mbps or 1.6 Gbps, and a plurality of address signals are transmitted at an extremely high transfer rate. It is, therefore, necessary for the internal serial/parallel converter to latch, in a short period of time, address signals which are input at high speed and to output them in parallel with the same phase.
FIG. 35 is a diagram illustrating a conventional serial/parallel converter. FIG. 36 is a timing chart for the serial/parallel converter in FIG. 35. In this example circuit, a clock CLK is amplified by a clock amplifier C36 and an internal clock S55 is generated. The internal clock S55 is divided by 4 by a frequency divider C45, and a clock S64 for final latching is generated. Input data DATA is amplified by a data amplifier C37, and is transferred to corresponding flip-flop circuits C38 through C44 at the leading edges or trailing edges of the internal clock S55. That is, the flip-clop circuits C38, C39, C40 and C41 latch the input data DATA at the leading edges of the internal clock S55, while the flip-flops C42, C43 and C44 latch the input data DATA at the trailing edges of the internal clock S55.
As is shown in FIG. 36, the data DATA is transmitted synchronously with the leading edges of the clock CLK (internal clock S55), and is synchronously latched by the flip-flops with the leading edges and the trailing edges of the internal clock S55. In this example circuit, at time T1, where data Dn, Dn+1, Dn+2 and Dn+3 are latched by the corresponding flip-flops C38, C39, C40 and C41, these data are latched by the flip-flops C46, C47, C48 and C49 at the leading edge of a final latch clock S64. During a period equivalent to four times the cycle of the clock CLK, the flip-flops C46 through C49 latch the data and output in parallel a set of four data (S65xcx9cS68)to four output terminals S65 through S68.
As is described above, the conventional serial/parallel converter converts four serial data sets into four parallel data sets in synchronization with the leading edge of the xc2xc frequency divided clock S64.
The above serial/parallel converter requires eleven flip-flop circuits for 4-bit serial/parallel conversion. In addition, since the flip-flops C38 through C44 perform data latching four times and the flip-flops C46 through C49 perform data latching one time, a total of 32 operations by the flip-flops are required for one conversion process, and the current consumption is increased. According to this, for the conversion of 8-bit serial data, the number of required flip-flop circuits and the number of operations will be increased and the current consumption will be also increased.
Further, when the frequency of the input clock is increased, the operation speed of the flip-flop that performs synchronous latching with the input clock has to correspond to that speed. Thus, the circuit must be so designed that it can be operated at a high speed with a higher current consumption. Therefore, when a large number of flip-flops are operated for one serial/parallel conversion, the current consumption will be further increased. In addition, for faster processing, a serial/parallel converter is required that can cope with the input of data synchronized with the leading edge and the trailing edge of the input clock.
The serial input data is supplied in synchronous with a flag signal indicating the head of the serial data, therefore it is required that a fetching of the serial input data should be initiated using the flag signal as a trigger, and a parallel data output should be output at a certain timing signal. However, it is not easy to generate the timing signal for parallel data output after the last serial data has been fetched. Especially difficult, while taking into account an operating delay time for a flip-flop circuit for fetching the last serial data, is generating a timing signal for parallel data output at the shortest timing.
In addition, a circuit is required which generates a control clock for fetching serial data using an externally supplied flag signal as a trigger. Since this circuit has its own operating delay time, the input of serial data synchronized with a fast clock is affected accordingly. Therefore, a circuit is required which can fetch serial data without being affected by the timing of a flag signal.
It is, therefore, one object of the present invention to provide a circuit which requires a smaller number of flip-flops and which performs serial/parallel conversion by using a smaller number of latch operations.
It is another object of the present invention to provide a serial/parallel converter which can even latch serial data synchronously with a faster input clock, and which consumes only a small amount of current.
It is an additional object of the present invention to provide a serial/parallel converter which can provide an optimal relationship between the timings for the termination of a serial data fetch process and the output of parallel data.
It is a further object of the present invention to provide a serial/parallel converter which can synchronize the fetching of serial data with a clock without being affected by the timing of a flag signal indicating the head of serial data.
To achieve the above objects, according to one aspect of the present invention, a serial/parallel converter, outputting, with the same phase and in parallel, a plurality of data which is input serially in synchronization with an input clock, comprises:
a pulse generator for generating a plurality of latch clocks synchronized respectively with input timings of the plurality of data;
a plurality of holding flip-flops for latching in order the plurality of data in response to the plurality of latch clocks; and
a plurality of output latch flip-flops for, in response to the last latch clock synchronized with input of the last data of the plurality of data, latching, in parallel, the plurality of data held by the holding flip-flops and the last input data.
According to the present invention, the number of required flip-flops can be reduced, and each flip-flop need perform latching only once for a single serial/parallel conversion, so that the amount of current consumption is reduced.
Further, to achieve the above objects, according to the second aspect of the present invention, a serial/parallel converter, outputting, with the same phase and in parallel, a plurality of data which is input serially in synchronization with an input clock, comprises:
at least two input latch flip-flops for latching the plurality of input data in synchronization with the input clock;
a pulse generator for generating a plurality of latch clocks synchronized with timings at which the plurality of data are held by the input latch flip-flops;
a plurality of holding flip-flips for latching in order the plurality of data held by the input latch flip-flops in response to the plurality of latch clocks; and
a plurality of output latch flip-flops for, in response to the last latch clock synchronized with the latching of the last data of the plurality of data to the input latch flip-flops, latching, in parallel, the plurality of data held by the holding flip-flops and the last data held by the input latch flip-flops.
In the above circuit, when the input latch flip-flops have a first latching speed and the holding flip-flops have a second latching speed lower than the first latching speed, the serial data transferred at high speed can be latched, and the total amount of current consumption can be reduced. The above circuit also needs only a small number of flip-flops and the amount of current consumption is small as the first invention.
To achieve the above objects, according to a third aspect of the present invention, a serial/parallel converter for converting N bits (N is a plural) of serial data, which are supplied in synchronization with a clock from a timing of a flag signal, into parallel data comprising:
a pulse generator for serially generating first to Nth timing pulses in synchronization with the clock;
a flag signal latch circuit for latching said flag signal in response to said first timing pulse and for outputting a strobe signal corresponding to said flag signal in response to said Nth timing pulse;
a first-stage latch circuit for latching first to (Nxe2x88x921)th serial data in response to said first to (Nxe2x88x921)th timing pulses;
a second-stage latch circuit for latching, in response to said Nth timing pulse, the serial data latched by said first-stage latch circuit as well as an Nth serial data; and
final-stage gate circuit for outputting in parallel N bits serial data latched by said second-stage latch circuit in response to said strobe signal.
According to the present invention, since the strobe signal is output in parallel to the latching of the serial data in the serial/parallel converter, the strobe signal can be generated at an optimal timing.
Also, to achieve the above objects, according to a fourth aspect of the present invention, a serial/parallel converter for converting N bits (N is a plural) of serial data, which are supplied in synchronization with a clock from a timing of a flag signal, into parallel data comprising:
a pulse generator for generating first to Nth timing pulses serially in synchronization with a clock;
a flag signal latch circuit for latching said flag signal in response to said first timing pulse and for outputting a strobe signal corresponding to said flag signal in response to said Nth timing pulse;
a first-stage latch circuit for latching a (2Mxe2x88x921)th serial data in response to a (2Mxe2x88x921)th (M are all integers of 1xe2x89xa6Mxe2x89xa6N/2) timing pulse;
a second-stage latch circuit for latching, in response to 2Mth timing pulse, said (2Mxe2x88x921)th serial data latched by said first-stage latch circuit as well as 2Mth serial data; and
final-stage gate circuit for outputting in parallel N bits of serial data latched by said second-stage latch circuit in response to said strobe signal.
According to this aspect, the strobe signal can be generated at an optimal timing.
In addition, to achieve the above objects, according to a fifth aspect of the present invention, a serial/parallel converter for converting N bits (N is a plural) of serial data, which are supplied in synchronization with a clock from a timing of a flag signal, into parallel data comprises:
a pulse generator for repeatedly generating first to Nth timing pulses serially in synchronization with a clock;
a flag signal latch circuit for latching said flag signal in response to a (2Ixe2x88x921)th (I are all integers of 1xe2x89xa6Ixe2x89xa6N/2) timing pulse and for outputting first to (N/2)th strobe signals corresponding to said flag signal in response to a (2Ixe2x88x922)th (or Nth if I=1) timing pulse;
a first-stage latch circuit for latching first to Nth serial data in response to said first to Nth timing pulses;
N/2 groups of second-stage latch circuits for respectively latching, in response to a (2Ixe2x88x922)th timing pulse, (2Ixe2x88x921)th to (2Ixe2x88x923)th ((Nxe2x88x921)th if I=1) serial data latched by said first-stage latch circuit; and
N/2 groups of final-stage gate circuits for respectively outputting in parallel, in response to said first to said (N/2)th strobe signals, (Nxe2x88x921) bits of serial data latched by said second-stage latch circuits as well as Nth serial data latched by said first latch circuit.
According to the fifth aspect, when the leading edge of a clock corresponds to the flag signal, appropriate serial data can be latched and output regardless of which leading edge of the clock it is at which the flag signal is supplied.
Furthermore, according to sixth aspect of the present invention a serial/parallel converter for converting N bits (N is a plural) of serial data, which are supplied in synchronization with a clock from a timing of a flag signal, into parallel data comprising:
a pulse generator for repeatedly generating first to Nth timing pulses serially in synchronization with a clock;
a flag signal latch circuit for latching said flag signal in response to an Ith (I are all integers of 1xe2x89xa6Ixe2x89xa6N) timing pulse and for outputting first to Nth strobe signals corresponding to said flag signal in response to an (Ixe2x88x921)th (or Nth if I=1) timing pulse;
a first-stage latch circuit for latching first to Nth serial data in response to said first to Nth timing pulses;
N groups of second-stage latch circuits for respectively latching, in response to said Ith timing pulse, Ith to (Ixe2x88x922)th ((Nxe2x88x921)th if I=1 and Nth if I=2) serial data latched by said first-stage latch circuit; and
N groups of final-stage gate circuits for outputting in parallel, in response to said first to said Nth strobe signals, (Nxe2x88x921) bits of serial data latched by said second-stage latch circuits as well as Nth serial data latched by said first latch circuit.
According to the sixth aspect, regardless of whether a flag signal is supplied at a leading edge of a clock or at a trailing edge, all the available sets of serial data can be latched and appropriate serial data can be output.
Moreover, according to a seventh aspect of the present invention, a serial/parallel converter for converting N bits (N is a plural) of serial data, which are supplied in synchronization with a clock from a timing of a flag signal, into parallel data comprising:
a pulse generator for repeatedly generating first to Nth timing pulses serially in synchronization with a clock;
a flag signal latch circuit for latching said flag signal in response to a (2Mxe2x88x921)th (M are all integers of 1xe2x89xa6Mxe2x89xa6N/2) timing pulse and for outputting first to (N/2)th strobe signals corresponding to said flag signal in response to a (2Mxe2x88x922)th (or Nth if M=1) timing pulse;
a first-stage latch circuit for latching a (2Mxe2x88x921)th serial data in response to said (2Mxe2x88x921)th (M is an integer of 1xe2x89xa6Mxe2x89xa6N/2) timing pulse;
a second-stage latch circuit for latching, in response to a 2Mth timing pulse, said (2Mxe2x88x921)th serial data latched by said first-stage latch circuit as well as a 2Mth serial data; and
N/2 groups of final-stage gate circuits for outputting in parallel, in response to said first to said (N/2)th strobe signals, N bits of serial data latched by said second-stage latch circuit.
According to the seventh aspect, when the leading edge of a clock corresponds to the flag signal, appropriate serial data can be latched and output regardless of which leading edge of the clock it is at which the flag signal is supplied.
To achieve the above objects, according to an eighth aspect of the present invention, a serial/parallel converter for converting N bits (N is a plural) of serial data, which are supplied in synchronization with a clock from a timing of a flag signal, into parallel data comprising:
a pulse generator for repeatedly generating first to Nth timing pulses serially in synchronization with a clock;
a flag signal latch circuit for latching said flag signal in response to an Mth (M are all integers of 1xe2x89xa6Mxe2x89xa6N) timing pulse and for outputting first to Nth strobe signals corresponding to said flag signal in response to a (Mxe2x88x921)th (or Nth if M=1) timing pulse;
first-stage latch circuits for respectively latching an Mth serial data in response to said Mth (M are all integers of 1xe2x89xa6Mxe2x89xa6N) timing pulse;
a second-stage latch circuit for latching, in response to an (M+1)th (first if M=N) timing pulse, said Mth serial data latched by said first-stage latch circuit; and
N groups of final-stage gate circuits for outputting in parallel, in response to said first to said Nth strobe signals, N bits of serial data latched by said first-stage and said second-stage latch circuits.
According to the eighth aspect, regardless of whether a flag signal is supplied at a leading edge of a clock or at a trailing edge, all the available sets of serial data can be latched and appropriate serial data can be output.